However, if you are targetting a specific clock period, doing this is not an option. Clock period: More is the clock period, more is the setup slack.Setup time requirement of capturing flip-flp: Less the setup time requirement, more will be setup slack.Clock skew: More the clock skew (difference between arrival times of clock at capture and launch flip-flops), more is the setup slack.
Data path delay: More the total delay of data path (flip-flop delay + combinational delay + Setup), less is setup slack.If we analyze setup equation more closely, it involves four parameters:
If, by chance, a fabricated design is found to have a setup violation, you can still run the design at less frequency than specified and get the desired functionality as setup equation includes clock period as a variable. On the other hand, a negative setup slack means setup violating timing path. If setup slack is positive, it means the timing path meets setup requirement. T ck->q + T prop + T setup - T skew q - T prop - T setup + T skew The timing equation for a setup check from positive edge-triggered flip-flop to positive edge-triggered flip-flop is given as below: Setup violations: As we know, setup checks are applied for timing paths to get the state machine to move to the next state. So, it is very important to have setup and hold requirements met for all the registers in the design and there should not be any setup/hold violations. Moreover, setup/hold violations can lead to data getting captured within the setup/hold window which can lead to metastability of the capturing flip-flop (as explained in our post metastability). Similarly, if hold check is violated, data intended to get captured at the next edge will get captured at the same edge. If the setup check is violated, data will not be captured properly at the next clock edge. In other words, no timing violations means that the data launched by one flip-flop at one clock edge is getting captured by another flip-flop at the desired clock edge. What if setup and/or hold violations occur in a design: As said earlier, setup and hold timings are to be met in order to ensure that data launched from one flop is captured properly at another and in accordance to the state machine designed.
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